1. Field of the Invention
This invention relates generally to the manufacture of high performance semiconductor devices and, more particularly, to the manufacture of high performance submicron semiconductor devices and, even more particularly, to a method for the manufacture of high performance submicron semiconductor devices to minimize dopant accumulation at the polysilicon-tunnel oxide interface.
2. Discussion of the Related Art
The semiconductor industry is characterized by the dual requirements of an increase in the speed of integrated circuits and an increase in the speed of integrated circuits and an increase in the density of elements in integrated circuits. Thus, these two requirements have become the two major goals of MOSFET scaling. Increasing the density of elements means, primarily, that smaller channel lengths and widths have to be used. Increasing the speed of integrated circuits means, primarily, that the MOSFET saturation drain current I.sub.DSAT must be increased to allow faster charging and discharging of parasitic capacitances. Existing performance models for MOSFETs predicted that a decrease in either the channel length, L, or the gate oxide thickness, t.sub.ox, would increase I.sub.DSAT. However, as device were scaled below approximately 2 microns, "short-channel" effects were observed that were not predicted by the existing performance models which were then referred to as "long channel" models. For example, one of the short channel effects that was not predicted by the long channel model was that I.sub.DSAT becomes independent of channel length in extremely small MOSFETs and approaches a constant value regardless of any decrease in the channel length. It was also found that decreasing the gate oxide thickness, t.sub.ox, provided a much greater increase in I.sub.DSAT than a concomitant decrease in channel length, L. However, a thinner gate oxide thickness, t.sub.ox, will cause I.sub.DSAT to increase faster to the constant value as the channel length, L, is decreased. Therefore, decreasing the gate thickness, t.sub.ox, results in an increase in I.sub.DSAT in two ways and, therefore, it was determined that it is more advantageous to concentrate on methods to decrease gate oxide thickness rather than on methods to decrease channel length.
As device dimensions continued to decrease, it was discovered that other short-channel effects needed to be addressed. All of the short-channel effects were placed into the following two general categories: (1) the problem of increased leakage current when the MOSFET is off and (2) reliability problems associated with short-channel and thin gate oxide device structures.
The reliability problems that arise in short-channel and thin gate oxide MOSFETs include: (1) thin gate oxide breakdown; (2) device degradation due to hot-carrier effects; and (3) reliability problems associated with interconnects between MOSFETs. The problems that are of interest are the phenomena of thin gate oxide breakdown and the phenomena of device degradation due to contamination of the gate/gate oxide region, and more specifically, the gate/gate oxide interface.
The characteristics of the Si--SiO.sub.2 interface in a MOSFET determine, to a significant extent, the functioning of the gate dielectric. Similarly, the interface between the polysilicon gate and the gate oxide determine, to a significant extent, the functioning of the gate dielectric. A study of the structure of the gate/gate oxide interface has resulted in the identification of device degradation effects caused by the accumulation of dopant atoms at the gate/gate oxide interface. In addition, because of defects or faults that exist in prior art devices that are exacerbated by the conventional method of growing a polysilicon. The trend in the semiconductor industry has been to deposit a layer of amorphous silicon in an attempt to obtain conformality of the gate layer over the faults that exist at the gate/gate oxide interface. FIG. 8 illustrates a conventional method of forming a layer of amorphous silicon 802 on the layer of gate oxide 702. A stream of silane, indicated by arrows 800 is directed towards the gate oxide layer 702. A dopant is injected into the silane stream to dope, in situ, the amorphous silicon. As is known in the art, the device is later annealed at a temperature to form polysilicon from the amorphous silicon layer. One such dopant is phosphene which provides phosphorous atoms as the dopant material in the gate. Because the gates have become ultrathin for reasons discussed above, the control of the doping concentrations at various depths in the gate have become very difficult. The ultrathin gates, gate oxide layers, and other elements in the semiconductor device have made problems associated with contaminants more apparent and have made semiconductor devices more susceptible to degradation and failure because of contamination levels that were acceptable in prior devices. The conventional method shown in FIG. 8 introduced phosphene in a concentration to "lightly" dope the amorphous silicon gate material because more than a "lightly" doped material would cause uneven accumulation in an anneal step or a post anneal process. The difficultly of controlling the concentration is primarily due to the fact that the gate is scaled to submicron levels. However, the "lightly" doped gate region has resulted in a P depletion effect in the gate which will affect operating parameters of the device. In memory devices, a high concentration of P degrades the gate oxide and cause devices, such as memory devices, particularly flash memory devices to degrade and fail.
What is needed is a method of manufacturing a semiconductor device that has a properly doped gate without having unwanted dopant concentrations at the gate/gate oxide interface.